1. Field of the Invention
The present invention relates to a frame transfer system CCD solid-state image pickup device and an operation method of the solid-state image pickup device.
2. Description of the Related Art
Electronic still cameras using solid-state image pickup devices have been utilized as means for introducing image information into a computer device such as a personal computer or a word processor. These electronic still cameras are constituted so that an object image can be picked up as an animated image, i.e., the continuum of static images and the image information of one desired image frame can be fetched from these images in the same manner as in a conventional image pickup device such as a television camera. Usually, in the processing of the image information of such an electronic still camera, in order to speed up the processing, the continuous images are reproduced with image signals of information reduced by appropriately thinning out the image information, and complete signal processing is conducted only for the image information of one image frame to be finally fetched.
FIG. 1 is a block diagram showing a constitution of a conventional electronic still camera.
A CCD solid-state image pickup device 1 includes a plurality of light receiving elements arranged in matrix and shift registers associated with the light receiving elements. A plurality of light receiving elements generate information charges in response to light of the object image which is radiated to a light receiving surface by a known lens mechanism, and these elements independently accumulate the information charges. The shift register transfers and outputs the information charges accumulated in each light receiving element in a predetermined sequence. Additionally, in the solid-state image pickup device 1, the output end of the shift register is provided with a capacity for accumulating the information charge in a unit of picture element. The amount of the transferred and emitted information charges is converted to a voltage value, which is fetched and emitted as an image signal Y0(t).
A drive circuit 2 supplies multiphase vertical transfer clock φv and horizontal transfer clock φh to the shift registers of the solid-state image pickup device 1 to transfer and output the information charges accumulated in a plurality of light receiving elements in the predetermined sequence. Specifically, the information charges of each light receiving element is transferred to the shift register according to a vertical scanning timing and subsequently transferred/output line by line according to a horizontal scanning timing, so that the continuous image signal Y0(t) in a line unit can be obtained. A timing control circuit 3 generates a horizontal synchronous signal HT and a vertical synchronous signal VT based on a reference clock of a constant cycle, and supplies the signals to the drive circuit 2. The horizontal and vertical synchronous signals HT and VT determine the horizontal and vertical scanning timings of the solid-state image pickup device 1, and are generated according to a predetermined format. Simultaneously, a timing signal PC for standardizing the image signal Y0(t) according to the horizontal and vertical synchronous signals HT and VT is generated and supplied to a signal processing circuit 4 to be described later. Additionally, the timing control circuit 3 responds to an image defining instruction DI to stop the drive circuit 2 from its continuous image pickup operation and to allow the signal processing circuit 4 to output image data D(n) of one specific image frame corresponding to the image signal Y0(t).
The signal processing circuit 4 takes the image signal Y0(t) output from the solid-state image pickup device 1, applies various processings such as sample holding, level correction and the like in accordance with the timing signal PC, and supplies an image signal Y1(t) according to the predetermined format to a display 5. The signal processing circuit 4 includes an A/D converter and a D/A converter, in which the image signal Y0(t) is subjected to a signal processing as digital data, reset to the analog-value image signal Y1(t) after the predetermined signal processing is completed, and supplied to the display 5. Furthermore, the digital image data D(n) for one image frame of the image signal Y0(t) when the timing control circuit 3 receives the image defining instruction DI is supplied to the outside as a static image output by the signal processing circuit 4. The display 5 is constituted of, for example, an LCD panel for continuously displaying the image picked, up by the solid-state image pickup device 1 in accordance with the image signal Y1(t) supplied from the signal processing circuit 4. Additionally, after the image defining instruction DI is received, a static image of the image data D(n) emitted as the static image output is displayed.
FIG. 2 is a schematic diagram showing the constitution of the CCD solid-state image pickup device 1 in a frame transfer system. In FIG. 2, for the sake of simplicity, the arrangement of light receiving elements is shown as a pattern of 12 lines by 16 columns. FIG. 3 is a timing chart showing the relationship of each transfer clock and each synchronous signal for operating the solid-state image pickup device 1.
The frame transfer system CCD solid-state image pickup device 1 comprises an image pickup section 1i, a storage section 1s, a horizontal transfer section 1h and an output section 1d. The image pickup section 1i comprises a plurality of vertically continuous and mutually parallel CCD shift registers, and each bit of the shift registers constitutes each light receiving element. Frame transfer clocks φf1 to φf3 synchronous with the vertical synchronous signal VT are applied to the image pickup section 1i, and the information charges accumulated in each light receiving element during the image pickup period are transferred to the storage section 1s at a high rate in a vertical-scanning blanking period.
The storage section 1s continues from the shift registers of the image pickup section 1i, and comprises a plurality of CCD shift registers coincident in bit number. Each bit of the shift registers constitutes a storage picture element, in which the information charges transferred/emitted from each light receiving element of the image pickup section 1i are temporarily accumulated. Vertical transfer clocks φv1 to φv3 synchronous with the vertical and horizontal synchronous signals VT and HT are applied to the storage section 1s, so that the information charges for one image frame are taken from the image pickup section 1i. Additionally, the taken information charges are transferred by a unit of one line to the horizontal transfer section 1h in a horizontal-scanning blanking period.
The horizontal transfer section 1h is constituted of a single CCD shift register having each bit coupled to the output of each shift register of the storage section 1s, and each bit receives the information charges transferred/emitted from each shift register of the storage section 1s. Horizontal transfer clocks φh1 and φh2 synchronous with the horizontal synchronous signal HT are applied to the horizontal transfer section 1h, so that the information charges transferred/emitted from each shift register of the storage section 1s are successively transferred by a unit of horizontal line to the output section 1d. 
The output section 1d is able to receive information charges on the output side of the horizontal transfer section 1h, and subsequently outputs a voltage value corresponding to the amount of electric charge upon receipt of the information charges transferred/emitted from the horizontal transfer section 1h. A reset clock φr is applied to the output section 1d in accordance with the horizontal transfer clocks φh1 and φh2. By discharging the information charges successively transferred/emitted from the horizontal transfer section 1h by a unit of picture element, the voltage value corresponding to the amount of the information charges for each picture element is fetched. Here, a change of the emitted voltage value forms the image signal Y0(t).
In the frame transfer system solid-state image pickup device 1, since the storage section 1s for temporarily accumulating the information charge which is obtained by picking up the image is apart from the light receiving elements of the image pickup section 1i, there is only slight leakage of unnecessary electric charges from the light receiving elements. Therefore, the solid-state image pickup device 1 is suitable for an electronic still camera which reads information charges from the solid-state image pickup device at arbitrary timings to obtain static images.
In the electronic still camera described above, an animated image is fetched by continuously operating the solid-state image pickup device 1, and a desired static image can be fetched while observing the animated image. At that time, since the animated image forms only a confirming image frame, it need not be of high quality. Usually, by decreasing the information amount of the image signal Y0(t) beforehand, the signal processing in the signal processing circuit 4 is simplified. Specifically, by thinning out the image signal Y0(t) by a constant unit of column or line in the input stage of the signal processing circuit 4 to decrease the information amount, various signal processings can be simplified and speeded up.
However, the constitution for thinning out the image signal Y0(t) in the signal processing circuit 4 speeds up the circuit operation of the input section to increase the power consumption, and also results in an increase of cost because the circuit itself easily becomes large-scaled.